This invention relates to charge coupled devices, and more particularly to charge coupled devices having extremely small geometries which are readily reproducible with a relatively high yield. Charge coupled devices are basically comprised of a semiconductor substrate having dopant impurity atoms of one type and a first surface. A charge transfer channel lies in the substrate near the first surface. An insulating layer lies on the first surface; and a plurality of electrodes lie spaced apart from each other on the insulating layer traversely to the charge transfer channel. Clocking voltages are applied to the electrodes to generate moving potential wells under the electrodes. Charge packets of minority charge carriers representing sampled analog signals or digital "bits" are propagated along the charge transfer channel in the potential wells.
In the past, the above generally described structure for a charge coupled device has been modified into various new and non-obvious structures. For example, some prior art charge coupled devices have relatively "flat" electrodes, have an insulating layer of a uniform thickness under all of the electrodes, and have regions of immobile charges in the substrate to form asymmetric potential wells under each electrode. In other charge coupled devices, each electrode is "stepped", the insulating layer under each of the electrodes is of a stepped thickness, and the stepped thickness forms asymmetric potential wells under the electrodes. As an example of the former structure, see U.S. Pat. No. 3,660,697 issued May 2, 1972, to Berglund et al, entitled, "Monolithic Semiconductor Apparatus for Sequential Charge Transfer". As an example of the latter structure, see U.S. Pat. No. 3,651,349 issued May 21, 1972 to Kahng et al, and having the same title.
The embodiments disclosed in the above references, along with other prior art embodiments work fine for packaging densities that are relatively small --that is, no larger than 16,000 bits per chip. However, they are not suitable for use in ultra-high density packages, such as memories containing from 256,000 bits per chip to 1,000,000 bits per chip. The "flat" electrode structure is more suitable for high density packages than the "stepped" electrode structure, because it yields a smaller cell size for any given minimum length dimension of the electrodes. But the "flat" electrode structure is unsuitable for high density packages because as the dimensions of the electrodes, the insulating layer, and the spaces between alternate electrodes is reduced (in order to get more bits of storage per unit area) the % yield of good chips to bad chips is also reduced. And when the dimensions are reduced to the point required to package 64,000 bits per chip, the % yield becomes so small as to make large scale manufacturing impractical. Chips of 64K bits require a uniform insulating layer thickness of approximately 1,000 angstroms and an inter-electrode spacing of approximately 1,000 angstroms. With these dimensions, yields of 2%-10% are not uncommon.
Despite this problem, however, there is a large need for decreasing the geometries of charge coupled devices. For example, the history of the computer industry indicates a continual demand for larger and cheaper memories. Accordingly, the applicants have investigated the problem and discovered that a large percentage of the failures (50%-80%) are due to inter-electrode shorts. These shorts occur at random in the spaces between consecutive electrodes. These spaces are intended to be filled with an insulating layer; but the spaces are so small in chips containing 256,000 bits or more, that various process steps can--and often do--eliminate one or more of them. The exact process by which this occurs is disclosed in greater detail in conjunction with the description of the invention.
Accordingly, it is one object of the invention to provide a new and non-obvious charge coupled device structure.
Still another object of the invention is to provide a charge coupled device structure having geometries which are readily fabricated in an ultra high density package with relatively few inter-electrode shorts.